US CHIPS Act Funding Progress: Fab Construction Milestones and Workforce Constraints

Executive Summary

The CHIPS and Science Act has moved the US semiconductor fab buildout from announcement into partial production, but the programme's most consequential projects remain years from volume output. TSMC's Arizona Fab 21 Phase 1 became the first sub-5nm facility on American soil in late 2024, and Intel's Chandler Fab 52 entered high-volume production on the 18A node in late 2025, a genuine milestone. Yet the same period saw Intel delay its Ohio campus to 2030, Micron push its New York megafab first production date to 2030, and Samsung's Taylor fab struggle to secure foundry customers. Building a fab in the United States takes roughly 38 months and costs roughly twice as much as in Taiwan, according to Manufacturing Dive, and neither the construction-labour pipeline nor the specialised operational workforce is remotely close to keeping pace with announced capacity. The interplay between geopolitical urgency and domestic structural constraints creates both the programme's greatest strategic value and its most persistent execution risk.

The Two-Speed Programme: Where Production Is Real And Where It Remains Theoretical

The CHIPS Act programme has, as of mid-2026, produced two genuine operational milestones: TSMC's 4nm output in Arizona and Intel's 18A output in Chandler. Both carry strategic weight. TSMC's first Arizona fab is delivering "tens of millions" of Apple Silicon chips annually, with over 100 million chips planned for 2026, according to Blackridge Research. For Nvidia, TSMC's Fab 21 Phase 1 is providing a domestic source for Blackwell AI accelerator production, materially reducing the company's single-point-of-failure exposure to the Taiwan Strait. The interplay between geopolitical risk reduction and commercial chip output is what makes these two facilities the programme's clearest early returns.

Intel's position is structurally different. Fab 52's 18A capability is real, Tom's Hardware confirmed in June 2026 that it became fully operational in October 2025 as the first high-volume home of Intel 18A, producing Panther Lake compute tiles. The CHIPS programme converted $5.7 billion in unpaid Intel grants into a 9.9 percent equity stake, restructuring the funding relationship in a way that aligns government returns with the company's commercial success. Yet the foundry opportunity 18A represents depends entirely on yield progression: Intel has indicated industry-yields will not arrive before early 2027, and external customers including Microsoft have commitments contingent on 18A performance at volume scale. Taken together, these developments place Intel at a pivot point where the physical capability exists but the commercial validation remains six to twelve months away.

The programme's slower tier, Ohio, New York, Taylor, is characterised by a shared dynamic: announced investment commitments remain credible, but the conversion to operating fabs has slipped consistently toward the end of the decade. Intel's Ohio delay, as described by Intel's chief global operations officer Naga Chandrasekaran in a message to employees, reflects a "prudent approach to ensure we complete the project in a financially responsible manner," with acceleration contingent on customer demand. Samsung's Taylor, Texas situation is more acute: Tom's Hardware and Nikkei Asia have both reported supply chain executive concerns that customer demand for the originally planned 4nm process node is insufficient, pushing Samsung toward an upgrade to 2nm but complicating the path to CHIPS Act disbursement, which requires the facility to be operational. The broader geopolitical dynamics compound this uncertainty, as the interplay between US export control policy and Samsung's relationships with Chinese customers has created demand-side ambiguity that is not purely a construction problem.

The Workforce Bottleneck: Three Distinct Pipelines, Three Distinct Failures

McKinsey's research on US semiconductor workforce constraints frames the problem in a way that most CHIPS Act coverage misses: construction craft workers, fab technicians, and process engineers are sourced from entirely different talent pools, each facing shortages driven by different structural causes. This distinction matters because a policy or training programme that addresses one pool does nothing for the others.

For construction craft workers, welders, pipefitters, electricians, concrete specialists, the semiconductor demand spike overlaps with a broader US construction labour deficit that predates the CHIPS Act. McKinsey documented that unfilled construction jobs exceeded 400,000 before the Bipartisan Infrastructure Law and the Inflation Reduction Act injected more than a trillion dollars into concurrent infrastructure projects. Semiconductor fabs entered this already-constrained environment and competed directly with highway, grid, and data-centre construction for the same tradespeople. Tom's Hardware's reporting on the Arizona market documented that five TSMC and Intel suppliers had postponed or scaled back their own Arizona construction because of rising costs and labour shortages, a cascading effect where the primary fabs constrain their own ecosystem partners.

For fab technicians and process engineers, the SIA-Oxford Economics study is the most authoritative published source. The projected 67,000 unfilled positions by 2030 break into approximately 26,400 technician roles (certificates or two-year degrees), 27,300 engineering roles (four-year degrees), and 13,400 computer-science roles (advanced degrees). The Semiconductor Industry Association's 2026 Workforce Policy Blueprint noted that international students constitute 60 percent of all advanced degree graduates in semiconductor-relevant engineering and computer science fields at US universities, creating a structural dependency on immigration policy that Sourceability characterised as a geopolitical vulnerability of its own: "A fab in the US that must rely on foreign engineers to operate is still geopolitically vulnerable, just in a different way."

TSMC's Arizona experience illustrated the human dimension of this bottleneck with clarity. Fortune and Axios Phoenix reported that skilled-worker shortages were cited explicitly as a cause for the initial delays. TSMC's response, a Technician Apprenticeship Program and a 10-day Semiconductor Technician Quick Start programme run with Maricopa Community Colleges, represents a credible near-term mitigation but does not address the generation-long STEM pipeline problem. The Harvard Business School Institute for Business in Global Society noted in a February 2026 analysis that "without enough skilled workers, timelines keep slipping, costs definitely rise and the companies face real challenges in meeting their goals," quoting SEMI vice president Shari Liss directly.

McKinsey's survey data adds a further complication: in 2023, 53 percent of semiconductor employees were "at least somewhat moderate-to-high confidence" to resign within the following half-year, up from 40 percent in 2021, according to IEEE Spectrum. This attrition trend, if it continued into the CHIPS era, would mean that companies are simultaneously trying to staff newly built fabs while losing experienced workers from existing facilities, a stock-and-flow problem where the replacement rate for departing workers is competing for the same talent pool as the ramp-up demand from new construction.

The Materials Layer: Polysilicon, Process Gases, And The Critical Minerals Dependency

The workforce debate dominates public commentary on CHIPS Act execution risk, but a quieter materials vulnerability is developing in parallel. US domestic semiconductor fab construction requires not just skilled humans but highly specialised physical inputs: ultra-high-purity process gases (hydrogen fluoride, nitrogen trifluoride, ammonia), polysilicon, photomasks, and substrates for advanced packaging. Most of these inputs remain concentrated in Asia, and the supply chains that would underpin a domestically sovereign US fab ecosystem do not yet exist at the required scale.

Semiconductor Engineering's annual global fabs report highlighted the Hemlock Semiconductor polysilicon situation as a concrete example. A Michigan state committee withdrew $40 million in state support for Hemlock's hyper-pure polysilicon facility, while the federal CHIPS allocation of $325 million remained in limbo as of the report's April 2026 publication date. Polysilicon at the purity levels required for semiconductor fabrication, distinct from solar-grade polysilicon, is an area where US domestic capacity is genuinely insufficient for the planned fab buildout, and the absence of a funded domestic supplier compounds the supply-chain concentration risk that the CHIPS Act was partly designed to reduce.

The broader critical minerals dimension spills into the geopolitical domain. China's layered export controls, which Discovery Alert documented progressing through gallium and germanium to heavy rare earths and materials including tungsten, indium, and molybdenum, create a time-bounded pressure window. These controls, modelled partly on the US Foreign Direct Product Rule, are now extraterritorial in reach and apply to non-Chinese manufacturers that use Chinese-origin materials above defined thresholds. For US fab operators, the practical consequence is materials procurement complexity that raises costs and extends lead times, economic impacts on the supply chain that compound the existing construction-cost disadvantage relative to Taiwan and Korea.

The broader strategic and systemic implications include a scenario where US fabs achieve construction completion on schedule but cannot reach full-yield production because critical process materials are unavailable or priced above projections. This risk is distinct from workforce risk and requires a separate policy response, yet the current CHIPS funding structure does not prominently address upstream materials capacity with the same urgency as fab construction incentives.

Counterarguments

1. The delay pattern may reflect rational capital management rather than structural programme failure. Intel's Naga Chandrasekaran explicitly framed the Ohio slowdown as a financially responsible decision tied to customer demand signals, not a failure to execute. Micron similarly reallocated CHIPS funding to its Idaho facility where demand is more immediate. If one reads the delay pattern as disciplined sequencing, producing in Arizona first, building Ohio when demand warrants, then the headline narrative of programme underperformance is misleading. The evidence that would strengthen or weaken this reading is whether Ohio construction accelerates materially once 18A yields normalise and external foundry commitments harden; that evidence does not yet exist.

2. The Taiwan construction-cost and timeline comparison systematically understates US-specific advantages. The 38-month vs. 20-month comparison cited by Manufacturing Dive treats all construction environments as equal except for regulatory and labour differences. Taiwan's faster timeline reflects decades of accumulated fab-adjacent infrastructure, contractor expertise, component supplier clustering, and utility provisioning experience that the US will partly replicate as the cluster matures. The Phoenix market, where TSMC and Intel are co-located, is already generating a denser supplier ecosystem than the comparison would suggest. A purely cost-per-chip-at-equivalent-node comparison also ignores the insurance premium that geography-diversified production commands in an era of Taiwan Strait risk, a premium that Apple, Nvidia, and Microsoft are implicitly paying through customer commitments to US-produced chips.

3. The workforce gap projections may overstate the risk because automation is changing the technician-to-wafer-start ratio faster than the models assumed. The SIA-Oxford Economics 67,000-figure was published in 2023 against a baseline that preceded the AI-driven acceleration of fab automation, including AI-assisted equipment monitoring, defect detection, and process control. If the industry can deliver higher wafer starts per technician through these tools, and Nvidia's stated ambition of providing entire AI systems to manufacturers suggests this is an intended direction, then the workforce gap narrows in absolute terms even if degree-completion rates remain flat. The evidence available does not confirm this offset is sufficient, but it is a genuine unknown that the published projections do not capture.

Indicators To Watch

Decision Relevance

Scenario A (~55%): Uneven but forward-moving execution, TSMC and Intel Arizona deliver, Ohio and New York push further right. The current two-speed pattern consolidates. TSMC reaches 3nm volume production in Arizona by mid-2027. Intel 18A yields normalise by Q2 2027, triggering Microsoft and Amazon foundry commitments. Ohio and New York remain post-2030 stories. Recommended: Technology companies dependent on AI chip supply should formalise dual-source agreements with TSMC Arizona now rather than waiting for Ohio capacity. Investors in the semiconductor equipment and materials sector should weight Arizona and Chandler exposure heavily; Ohio and New York exposure remains long-dated optionality, not near-term revenue.

Scenario B (~30%): Workforce and materials constraints materialise more acutely, causing broad schedule slippage across the programme. The SIA-Oxford Economics workforce gap arrives ahead of projections as construction-era craft workers exit and operational-era technicians fail to fill the pipeline fast enough. One or more CHIPS-funded facilities opens physically but operates at sub-50% capacity utilisation due to staffing. Samsung Taylor fails to secure anchor customers and delays indefinitely, forfeiting CHIPS Act disbursement. Recommended: Companies planning supply-chain diversification away from Taiwan should build an additional 12-18 months of buffer into their timelines. Policymakers should treat the December 2026 Section 48D construction-start deadline as a hard forcing function: any project not breaking ground before year-end loses the 35% tax credit, raising the effective cost of remaining projects by a meaningful margin.

Scenario C (~15%): Programme acceleration, TSMC and Intel unlock a virtuous cycle, attracting additional customers and compressing Ohio and New York timelines. Intel 18A yields normalise faster than guidance. Apple confirms a volume commitment to Intel Foundry for 2028 production (Wall Street Journal reported preliminary discussions in May 2025). The US government's equity stake in Intel creates political pressure to accelerate Ohio funding disbursement. TSMC announces additional equipment for Phase 2 that enables 2nm production earlier than the Phase 3 timeline. Recommended: In this scenario, the December 2026 Section 48D deadline becomes a major catalyst, companies should be watching for construction-start announcements in the September-December 2026 window as a signal of acceleration confidence.

Analytical Limitations

• The yield improvement data for Intel 18A rests on Intel's own statements and a single CNBC interview with the chief operations officer; independent third-party yield verification is not publicly available, and Intel's prior history with node delays warrants treating the published trajectory as optimistic until external customer shipments confirm it.

• Samsung Taylor's customer pipeline is known primarily through unnamed supply-chain executives cited by Nikkei Asia; the actual state of CHIPS Act disbursement negotiations between Samsung and the Commerce Department is not publicly documented, making any assessment of the Taylor timeline provisional.

• The 67,000 workforce gap figure from SIA-Oxford Economics was modelled against 2023 degree-completion and hiring data; it does not capture either the automation-driven changes in technician-to-output ratios or the potential impact of the Trump administration's immigration policies on international student retention, both of which could move the gap in either direction by tens of thousands of roles.

• Materials supply constraints for polysilicon, specialty gases, and critical mineral inputs are documented at the level of policy announcements and funding gaps, but actual fab-level procurement data, contracts, supplier commitments, inventory levels, is proprietary and not publicly available, creating a significant blind spot in assessing when and whether materials shortfalls will constrain production.

• This assessment does not cover classified national security dimensions of CHIPS Act implementation, including Secure Enclave provisions and Department of Defense microelectronics requirements, which are publicly acknowledged but not assessable from open sources.